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An Japan patent “Method of making a picoscopic scale/ nanoscopic scale circuit pattern” has been granted.

 

 

 

 

An Japan patent “Method of making a picoscopic scale/ nanoscopic scale circuit pattern” invented by the founder, Dr. Ko-Chen Fang, has been received a notice of allowance (Japan patent application number: CFP-032090). This patent is an advanced manufacturing process of circuit patterns, which breaks through the current manufacturing process of semiconductor IC chips, and makes the line spacing in the circuit pattern of IC chips range from several nanometers to 1 nanometer, and even as small as 0.1 nm, which is a picoscopic scale manufacturing process of IC chips. The size of 0.1 nm line spacing is about the diameter of an atom, which is equivalent to depict the electronic circuit on an atom. This is undoubtedly a huge innovation!

 

At present, TSMC and Samsung are still competing for the 3 nm chip manufacturing. However, 3nm refers to the width of the DS channel of a transistor. Their line spacing is still about 40 nm. In contrast, the manufacturing process of this patent can reduce the spacing between several nanometers and 0.1 nm. Besides, the extreme ultraviolet (EUV) lithography technology nowadays can provide a EUV having a wavelength of 13.5 nm, so it is impossible for EUV lithography to make picoscopic scale circuits directly.

 

Through this patented technology, the picoscopic scale/nanoscopic scale IC chips can be realized without using expensive photolithography machines and etching machines in the process, which is simple, cost-effective, and beneficial for mass production, has more potential for commercial implementation and will create a new situation for the semiconductor industry.

 

At present, the invention has been applied for patents in many countries, including Taiwan, China, US, Japan, South Korea, and Europe, wherein KR, EPC, Taiwan, US and Japan patents have been granted first, and other countries will be also certified successively.